Different techniques are used for defining fin structures of semiconductor device, as for instance semiconductor devices of the finfet type.
The dimensions and pitch of the fin structures (also called channels) of the finfet devices and pitches are following the ITRS roadmap and are getting smaller and smaller. Presently, a fin pitch of 10 nm (technology Node 10) can be achieved by advanced semiconductor processing techniques.
One of these techniques is known as the self-aligned double patterning (SADP) technique. This technique comprises the formation of dummy core structures, the sidewalls of which are foreseen by a spacer material, thereby resulting in narrow spacer structures surrounding the dummy core structures. The dummy core structures are then removed and the spacer structures are then disconnected by removing its end portions and patterned by means of a lithography step (a so-called “CUT lithography step”). The remaining very fine patterned spacer structures are then used as a mask for etching an underlying substrate to thereby define fin structures in the substrate for a finfet device, separated by narrow trenches.
The skilled person will appreciate that for still finer pitches, associated with fin pitches smaller than 10 nm, for instance 7 nm (technology Node 7, N7), the SADP technique seems to have reached its limits unless EUV lithography is used for defining the fin structures.
The EUV lithography technique has been considered a possible solution, but its insertion timing for high volume manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Therefore, use of SADP for technology nodes smaller than N10 is may not be advantageous.
Alternatively, another technique called Directed Self Assembly (DSA) can be used for the formation of fin structures smaller than those possible with the conventional lithography technique.
DSA is indicated as a potential method for CMOS integrated circuit patterning beyond the 10 nm node. The skilled person will appreciate that the application of this technique in CMOS still suffers from various disadvantages, some of which will be described below.
Thus, there exists a need for alternative techniques for producing fin structures of semiconductor devices, especially devices having fin pitch smaller than 10 nm (technology Node 10, N10).